S Sam Schiedermayer
Work in progress This is a Codex-built placeholder. The content and structure are still being developed and reviewed.
Learning series placeholder For software engineers

Software → Silicon

How hardware
gets made.

A practical guide to the people, tools, and decisions that turn an idea into a physical chip—written for people who already know how software gets built.

Explore the curriculum
Idea Architecture RTL Gates Layout Silicon

01 / The lifecycle

First, see the whole system.

Hardware development is not one job. This overview introduces the major disciplines, what each team owns, and how work moves between them.

  1. 01

    Define

    Product goals, workloads, requirements, constraints, and the business case.

    Think: product spec
  2. 02

    Architect

    System partitioning, interfaces, performance models, and microarchitecture.

    Think: system design
  3. 03

    Implement

    RTL design, IP integration, clocking, reset, power intent, and synthesis.

    Think: implementation
  4. 04

    Verify

    Simulation, formal methods, emulation, coverage, and system validation.

    Think: tests + CI
  5. 05

    Realize

    Floorplanning, placement, clock trees, routing, timing, and physical signoff.

    Think: build + deploy
  6. 06

    Validate

    Fabrication, bring-up, characterization, debug, yield, and production ramp.

    Think: production ops

02 / Idea to tapeout

Then, follow the work.

A sequential view of the development flow. Real projects overlap and loop constantly, but this path gives you a reliable mental model.

  1. 01

    Problem & requirements

    Define what the product must do and the power, performance, area, cost, and schedule it must meet.

    Plan
  2. 02

    System architecture

    Choose the major blocks, their responsibilities, interfaces, memory hierarchy, and data movement.

    Plan
  3. 03

    Microarchitecture

    Turn block-level intent into pipelines, state machines, queues, protocols, and cycle-level behavior.

    Design
  4. 04

    RTL implementation

    Describe the design in a hardware description language and integrate reusable intellectual property.

    Design
  5. 05

    Functional verification

    Prove the design behaves as intended with simulation, assertions, formal verification, and emulation.

    Prove
  6. 06

    Synthesis & DFT

    Map RTL into gates, close early constraints, and add structures that make manufactured chips testable.

    Build
  7. 07

    Physical design

    Place the gates, build the clock network, route the wires, and optimize the physical implementation.

    Build
  8. 08

    Signoff

    Check timing, power, signal integrity, reliability, and manufacturing rules across required conditions.

    Close
  9. 09

    Tapeout

    Freeze and release the final layout database to the foundry for mask generation and fabrication.

    Ship
  10. 10

    After tapeout

    Fabrication, packaging, first-silicon bring-up, validation, yield learning, and production ramp.

    Silicon

03 / Deep dives

Finally, go layer by layer.

This library will grow into focused articles and videos. Each collection is designed to stand alone while connecting back to the full development flow.

Collection 01Planned

Requirements &
architecture

Specifications, PPA tradeoffs, performance modeling, interfaces, and system partitioning.

  • 4 planned articles
  • Video series to come
Collection 02Planned

Microarchitecture
& RTL

Pipelines, state, timing, Verilog and SystemVerilog, clocking, reset, and power-aware design.

  • 6 planned articles
  • Hands-on examples
Collection 03Planned

Verification &
validation

Testbenches, constrained random testing, assertions, coverage, formal, emulation, and debug.

  • 5 planned articles
  • Video walkthroughs
Collection 04Planned

Synthesis &
physical design

Constraints, gates, floorplans, placement, clock-tree synthesis, routing, timing, and power.

  • 6 planned articles
  • Tool-flow diagrams
Collection 05Planned

Signoff &
tapeout

STA, physical verification, reliability, closure, foundry handoff, and the final release process.

  • 4 planned articles
  • Signoff checklists
Collection 06Planned

Silicon &
production

Fabrication, packaging, bring-up, post-silicon debug, characterization, yield, and product ramp.

  • 5 planned articles
  • Lab demos to come

An evolving resource

Start with the map.
Build the intuition.

Articles, diagrams, and video walkthroughs are coming. For now, use this curriculum as a map of the territory—and check back as each collection opens.

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